1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of preventing flicker or image-sticking and a driving method thereof.
2. Discussion of the Related Art
With the development of today's information society, demands for various display devices are increasing. To meet such demands, flat display devices, such as liquid crystal display devices (LCD), plasma display panels (PDP), and electroluminescent displays (ELD), have been developed, and some of them have been widely used.
Most of all, LCDs are lightweight and slim and have low power consumption. Also, LCDs may provide high image quality. Because of these advantages, CRTs have been replaced with LCDs. Such LCDs are widely used for notebook monitors, TV display panels, and so on.
The LCDs display images by controlling light transmittance of liquid crystal.
FIG. 1 is a schematic diagram of a related art LCD.
Referring to FIG. 1, the related art LCD includes a liquid crystal panel 2 in which pixel regions P are arranged in a matrix, a gate driver 4 for driving a plurality of gate lines GL0 to GLn of the liquid crystal panel 2, a data driver 6 for driving a plurality of data lines DL1 to DLm of the liquid crystal panel 2, and a timing controller 8 for controlling the gate driver 4 and the data driver 6.
In the liquid crystal panel 2, the gate lines GL0 to GLn and the data lines DL1 to DLm are arranged and thin film transistors (TFTs) and pixel electrodes (not shown) are formed at the crossings of the gate lines GL1 to GLn and the data lines DL1 to DLm. The pixel electrodes overlap common voltage lines VL1, VL2, . . . arranged in parallel to the gate lines GL1 to GLn, thereby forming storage capacitors Cst.
The gate driver 4 supplies scan signals to the gate lines GL1 to GLn in response to gate control signals generated from the timing controller 8. The data driver 6 supplies data voltages to the data lines DL1 to DLm in response to data control signals generated from the timing controller 8.
The timing controller 8 generates the control signals for controlling the gate driver 4 and the data driver 6 using vertical/horizontal sync signals (Vsync/Hsync), a data enable signal (DE), and a clock signal that are generated from an external system (not shown).
In such an LCD, the gate driver 4 supplies the liquid crystal panel 2 with the scan signals in response to the gate control signal supplied from the timing controller 8, and the data driver 6 supplies the liquid crystal panel 2 with the data voltage in response to the data control signal. Here, gray scale is reflected in the data voltage. Accordingly, the TFTs of the liquid crystal panel 2 are turned on and the data voltages are applied to the pixel electrodes through the turned-on TFTs. Although not shown, a predetermined common voltage is also applied to the common electrodes. Due to the difference between the data voltage and the common voltage, the liquid crystal is oriented and the light transmittance of the liquid crystal is controlled, thereby displaying the images.
When the TFT changes from the turned-on state to the turned-off state as the gate voltage changes from a high voltage (VGH) to a low voltage (VGL), the data voltage (Vd) charged at the pixel electrode is dropped as much as a kickback voltage (ΔVp) due to a parasitic capacitance (Cgs) of the TFT, as shown in FIG. 2.
The kickback voltage (ΔVp) is expressed in Eq. (1) below.
                              Δ          ⁢                                          ⁢                      V            p                          =                                            C              gs                                                      C                gs                            +                              C                st                            +                              C                                  1                  ⁢                                                                          ⁢                  c                                                              ⁢                      (                                          V                GH                            -                              V                GL                                      )                                              (        1        )            where                ΔVp is a kickback voltage        Cgs is a capacitance between a gate electrode (G) and a source electrode (S) in a TFT;        Cst is a storage capacitance;        Clc is a capacitance of a liquid crystal;        VGH is a gate high voltage; and        VGL is a gate low voltage.        
For example, it will be assumed that a positive data voltage is supplied during a positive polarity period, a negative data voltage is supplied during a negative polarity period, and the positive data voltage and the negative data voltage have the same gray scale. In this case, the positive data voltage during the positive polarity period and the negative data voltage during the negative polarity period are all dropped by the kickback voltage (ΔVp). Therefore, the difference between the common voltage and the positive data voltage during the positive polarity period is different from that between the common voltage and the negative data voltage during the negative polarity period. That is, different gray scales, not the same gray scales are displayed during the positive polarity period and the negative polarity period. Consequently, flicker and image-sticking occur due to the kickback voltage (ΔVp) on the liquid crystal panel 2, causing the degradation of the image quality.